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cy7c1062dv33 16-mbit (512 k 32) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 38-05477 rev. *h revised october 20, 2011 16-mbit (512 k 32) static ram features high speed ? t aa = 10 ns low active power ? i cc = 175 ma at 100 mhz low complementary metal oxide semiconductor (cmos) standby power ? i sb2 = 25 ma operating voltages of 3.3 0.3 v 2.0 v data retention automatic power down when deselected transistor-transistor logic (ttl) compatible inputs and outputs easy memory expansion with ce 1 , ce 2 , and ce 3 features available in pb-free 119-ball plastic ball grid array (pbga) package functional description the cy7c1062dv33 is a high per formance cmos static ram organized as 524,288 words by 32 bits. to write to the device, take chip enables (ce 1, ce 2, and ce 3 low) and write enable (we ) input low. if byte enable a (b a ) is low, then data from i/o pins (i/o 0 through i/o 7 ) is written into the location specified on the address pins (a 0 through a 18 ). if byte enable b (b b ) is low, then data from i/o pins (i/o 8 through i/o 15 ) is written into the location specified on the address pins (a 0 through a 18 ). likewise, b c and b d correspond with the i/o pins i/o 16 to i/o 23 and i/o 24 to i/o 31 , respectively. to read from the device, take chip enables (ce 1, ce 2 , and ce 3 low) and output enable (oe ) low while forcing the write enable (we ) high. if the first b a is low, then data from the memory location specified by the address pins appear on i/o 0 to i/o 7 . if b b is low, then data from memory appears on i/o 8 to i/o 15 . likewise, b c and b d correspond to the third and fourth bytes. see truth table on page 10 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 31 ) are placed in a high impedance state when the device is deselected (ce 1, ce 2, or ce 3 high), the outputs are disabled (oe high), the byte selects are disabled (b a-d high), or during a write operation (ce 1, ce 2 and ce 3 low and we low). logic block diagram column decoder row decoder sense amps input buffers 512 k x 32 array i/o 0 ?i/o 31 oe ce 3 b a b d output buffers control logic b b b c we ce 2 ce 1 a (9:0) a (18:10) [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 2 of 15 contents selection guide ................................................................ 3 pin configuration ............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics .......................................... 4 capacitance ...................................................................... 5 thermal resistance .......................................................... 5 ac test loads and waveforms ....................................... 5 ac switching characteristics ......................................... 6 data retention characteristics ....................................... 7 over the operating range ............................................... 7 data retention waveform ................................................ 7 switching waveforms ...................................................... 7 truth table ...................................................................... 10 ordering information ...................................................... 11 ordering code definitions ..... .................................... 11 package diagram ............................................................ 12 acronyms ........................................................................ 13 document conventions ................................................. 13 units of measure ....................................................... 13 document history ........................................................... 14 sales, solutions, and legal information ...................... 15 worldwide sales and design s upport ......... .............. 15 products .................................................................... 15 psoc solutions ......................................................... 15 [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 3 of 15 selection guide description -10 unit maximum access time 10 ns maximum operating current 175 ma maximum cmos standby current 25 ma pin configuration figure 1. 119-ball pbga (top view) [1] 234567 1 a b c d e f g h j k l m n p r t u i/o 12 i/o 16 i/o 17 i/o 18 i/o 19 i/o 27 i/o 23 i/o 25 aa aa ai/o 0 aa i/o 21 nc i/o 26 i/o 31 i/o 29 i/o 30 b c v ss v ss v dd v dd a v ss a a v dd ce 2 a ce 1 aai/o 1 nc ce 3 b a i/o 2 v ss v ss v ss v dd i/o 4 i/o 6 v ss v dd v dd v ss i/o 8 a a a i/o 15 oe v dd v ss v ss v dd v ss v ss v dd v ss b d v ss v dd v ss v ss i/o 5 v dd v ss v ss v ss nc v ss v dd v ss v ss v ss v ss v dd v ss v ss i/o 10 v dd i/o 14 i/o 13 a a v ss v ss v ss nc b b v dd i/o 3 we a i/o 20 v ss v dd i/o 22 v dd v ss i/o 7 v dd i/o 9 i/o 11 v dd v dd i/o 24 v ss i/o 28 v ss v dd v dd note 1. nc pins are not connected on the die. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 4 of 15 maximum ratings exceeding maximum ratings may shorten the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied .... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v cc relative to gnd [2] ................................?0.5 v to +4.6 v dc voltage applied to outputs in high z state [2] ................................ ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................. ?0.5 v to v cc + 0.5 v current into outputs (low) ........................................ 20 ma static discharge voltage (mil-std-883, method 3015) .................................. >2001 v latch-up current ..................................................... >200 ma operating range range ambient temperature v cc industrial ?40 ? c to +85 ? c 3.3 v ? 0.3 v dc electrical characteristics over the operating range parameter description test conditions [3] -10 unit min max v oh output high voltage min v cc , i oh = ?4.0 ma 2.4 ? v v ol output low voltage min v cc , i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 ? a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 ? a i cc v cc operating supply current v cc = max, f = f max = 1/t rc , i out = 0 ma, cmos levels ?175ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce > v ih , v in > v ih or v in < v il , f = f max ?30ma i sb2 automatic ce power-down current ? cmos inputs max v cc , ce > v cc ? 0.3 v, v in > v cc ? 0.3 v, or v in < 0.3 v, f = 0 ?25ma notes 2. v il(min) = ?2.0 v and v ih(max) = v cc + 2 v for pulse durations of less than 20 ns. 3. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 low. when high, ce indicates the ce 1, ce 2, or ce 3 high. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 5 of 15 capacitance parameter [4] description test conditions max unit c in input capacitance t a = 25 ? c, f = 1 mhz, v cc = 3.3 v 8 pf c out i/o capacitance 10 pf thermal resistance parameter [4] description test conditions 119-ball pbga unit ? ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board. 20.31 ? c/w ? jc thermal resistance (junction to case) 8.35 ? c/w ac test loads and waveforms figure 2. ac test loads and waveforms [5] 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf* (a) (b) r1 317 ? r2 351 ? fall time:> 1 v/ns (c) output 50 ? z 0 = 50 ? v th = 1.5 v 30 pf* *capacitive load consists of all components of the test environment rise time > 1 v/ns *including jig and scope notes 4. tested initially and after any design or proce ss changes that may affect these parameters. 5. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0 v). 100 ? s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0 v) voltage. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 6 of 15 ac switching characteristics over the operating range parameter [6] description -10 unit min max read cycle t power v cc (typical) to the first access [7] 100 ? ? s t rc read cycle time 10 ? ns t aa address to data valid ? 10 ns t oha data hold from address change 3 ? ns t ace ce active low to data valid [8] ?10 ns t doe oe low to data valid ? 5 ns t lzoe oe low to low z [9] 1? ns t hzoe oe high to high z [9] ?5 ns t lzce ce active low to low z [8, 9] 3? ns t hzce ce deselect high to high z [8, 9] ?5 ns t pu ce active low to power-up [8, 10] 0? ns t pd ce deselect high to power-down [8, 10] ?10 ns t dbe byte enable to data valid 5 ns t lzbe byte enable to low z [9] 1? ns t hzbe byte disable to high z [9] ?5 ns write cycle [11, 12] t wc write cycle time 10 ? ns t sce ce active low to write end [8] 7? ns t aw address setup to write end 7 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 7? ns t sd data setup to write end 5.5 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low z [9] 3? ns t hzwe we low to high z [9] ?5 ns t bw byte enable to end of write 7 ? ns notes 6. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, and input pulse levels of 0 t o 3.0v. test conditions for the read cycle use output loading as shown in (a) of figure 2 on page 5 , unless specified otherwise. 7. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 8. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 low. when high, ce indicates the ce 1, ce 2, or ce 3 high. 9. t hzoe , t hzce , t hzwe , t hzbe , t lzoe , t lzce , t lzwe , and t lzbe are specified with a load capacitance of 5 pf as in (b) of figure 2 on page 5 . transition is measured 200 mv from steady state voltage. 10. these parameters are guaranteed by design and are not tested. 11. the internal write time of the memory is defined by the overlap of ce 1 low, ce 2 low, ce 3 low and we low. chip enables must be active and we must be low to initiate a write, and the transition of any of these signals terminate the write. the input data setup and hold timing are r eferenced to the leading edge of the signal that terminates the write. 12. the minimum write cycle time for write cycle no.2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 7 of 15 data retention characteristics over the operating range parameter description conditions [13] min typ [14] max unit v dr v cc for data retention 2 ? ? v i ccdr data retention current v cc = 2 v, ce > v cc ? 0.2 v, v in > v cc ? 0.2 v, or v in < 0.2 v ?? 25 ma t cdr [15] chip deselect to data retention time 0??ns t r [16] operation recovery time t rc ??ns data retention waveform figure 3. data retention waveform 3.0 v 3.0 v t cdr v dr > 2v data retention mode t r ce v cc switching waveforms figure 4. read cycle no. 1 (address transition controlled) [17, 18] previous data valid data out valid rc t aa t oha t rc address data i/o notes 13. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 low. when high, ce indicates the ce 1, ce 2, or ce 3 high 14. typical values are included for reference only and are no t guaranteed or tested. typical values are measured at v cc = v cc(typ) , t a = 25 c. 15. tested initially and after any design or proc ess changes that affects these parameters. 16. full device operation requires linear v cc ramp from v dr to v cc(min) > 50 ? s or stable at v cc(min) > 50 ? s. 17. device is continuously selected. oe , ce , b a , b b , b c , b d = v il . 18. we is high for read cycle. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 8 of 15 figure 5. read cycle no. 2 (oe controlled) [19, 20, 21] figure 6. write cycle no. 1 (ce controlled) [19, 21, 22, 23] switching waveforms (continued) 50% 50% data out valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t hzbe t pd t dbe t lzbe t hzce oe ce address data i/o v cc supply b a , b b , b c , b d current high impedance i cc i sb t hd t sd t sce t sa t ha t aw t pwe t wc bw t data i/o address ce we b a , b b , b c , b d data in valid notes 19. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 low. when high, ce indicates the ce 1, ce 2, or ce 3 high. 20. we is high for read cycle. 21. address valid before or similar to ce transition low. 22. data i/o is high impedance if oe or b a , b b , b c , b d = v ih . 23. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 9 of 15 figure 7. write cycle no. 2 (we controlled, oe low) [24, 25, 26, 27] figure 8. write cycle no. 3 (b a , b b , b c , b d controlled) [24] switching waveforms (continued) t hd t sd t sce t ha t aw t pwe t wc t bw t sa t lzwe t hzwe data i/o address ce we b a , b b , b c , b d data in valid t hd t sd t bw t sa t ha t aw t pwe t wc t sce data i/o address b a , b b , b c , b d ce we data in valid notes 24. ce indicates a combination of all three chip enables. when active low, ce indicates the ce 1 , ce 2 , and ce 3 low. when high, ce indicates the ce 1, ce 2, or ce 3 high. 25. address valid before or similar to ce transition low. 26. data i/o is high impedance if oe or b a , b b , b c , b d = v ih . 27. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 10 of 15 truth table ce 1 ce 2 ce 3 oe we b a b b b c b d i/o 0 ?i/o 7 i/o 8 ?i/o 15 i/o 16 ?i/o 23 i/o 24 ?i/o 31 mode power h x x x x x x x x high z high z high z high z power-down (i sb ) x h x x x x x x x high z high z high z high z power-down (i sb ) x x h x x x x x x high z high z high z high z power-down (i sb ) l l l l h l l l l data out data out data out data out read all bits (i cc ) l l l l h l h h h data out high z high z high z read byte a bits only (i cc ) l l l l h h l h h high z data out high z high z read byte b bits only (i cc ) l l l l h h h l h high z high z data out high z read byte c bits only (i cc ) l l l l h h h h l high z high z high z data out read byte d bits only (i cc ) l l l x l l l l l data in data in data in data in write all bits (i cc ) l l l x l l h h h data in high z high z high z write byte a bits only (i cc ) l l l x l h l h h high z data in high z high z write byte b bits only (i cc ) l l l x l h h l h high z high z data in high z write byte c bits only (i cc ) l l l x l h h h l high z high z high z data in write byte d bits only (i cc ) l l l h h x x x x high z high z high z high z selected, outputs disabled (i cc ) l l l x x h h h h high z high z high z high z selected, outputs disabled (i cc ) [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 11 of 15 ordering information speed (ns) ordering code package diagram package type operating range 10 cy7c1062dv33-10bgi 51-85115 119-ball plastic ba ll grid array (14 22 2.4 mm) industrial cy7c1062dv33-10bgxi 119-ball plastic ball grid array (14 22 2.4 mm) (pb-free) ordering code definitions temperature range: i = industrial pb-free package type: bg = 119-ball pbga speed: 10 ns voltage range: v33 = 3 v to 3.6 v process technology: d = c9, 90 nm data width: 2 = 32-bits 06 = 16-mbit density 1 = fast asynchronous sram family technology code: c = cmos marketing code: 7 = sram company id: cy = cypress c cy 1 - 10 bg 7 06 d i v33 2 x [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 12 of 15 package diagram figure 9. 119-ball pbga (14 22 2.4 mm) bg119 package outline, 51-85115 51-85115 *c [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 13 of 15 acronyms document conventions units of measure acronym description ce chip enable cmos complementary metal oxide semiconductor i/o input/output oe output enable pbga plastic ball grid array sram static random access memory ttl transistor-transistor logic we write enable symbol unit of measure c degree celsius mhz megahertz ? a microampere ? s microsecond ma milliampere ns nanosecond ? ohm % percent pf picofarad v volt w watt [+] feedback
cy7c1062dv33 document number: 38-05477 rev. *h page 14 of 15 document history document title: cy7c1062dv33, 16-mbit (512 k 32) static ram document number: 38-05477 rev. ecn no. orig. of change submission date description of change ** 201560 swi see ecn advance data sheet for c9 ipp *a 233748 rkf see ecn ac, dc parameters are modified as per eros (spec # 01-2165) pb-free offering in the ordering information *b 469420 nxr see ecn converted from advance information to preliminary removed ?8 and ?12 speed bins from product offering removed commercial operating range changed j7 ball of pbga from dnu to nc in the pinout diagram included the maximum ratings for static discharge voltage and latch up current on page 2 changed i cc(max) from 220 ma to 150 ma changed i sb1(max) from 70 ma to 30 ma changed i sb2(max) from 40 ma to 25 ma specified the overshoot s pecification in footnote 1 changed t sd from 5.5 ns to 5 ns added data retention characteristics table and waveform on page 5. updated the 48-pin fbga package updated the ordering information table *c 499604 nxr see ecn added note 1 for nc pins updated test condition for i cc in dc electrical characteristics table added note for t ace , t lzce , t hzce , t pu , t pd , and t sce in ac switching characteristics table on page 4 *d 1462583 vkn / aesa see ecn converted from preliminary to final updated block diagram changed i cc spec from 150 ma to 175 ma updated thermal specs *e 2541850 vkn / pyrs 07/22/08 added -10bgi part in the ordering information table *f 3109102 aju 12/13/2010 added ordering code definitions . updated package diagram . *g 3137613 pras 01/13/2011 added acronyms and units of measure . updated datasheet as per template updated all footnotes sequentially *h 3416006 tava 10/20/2011 updated features . updated dc electrical characteristics . updated switching waveforms . updated in new template. [+] feedback
document number: 38-05477 rev. *h revised october 20, 2011 page 15 of 15 all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1062dv33 ? cypress semiconductor corporation, 2004-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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